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e product preview june 1999 order number: 290666-003 16-mbit flash + 2-mbit sram -- 28f1602c3 32-mbit flash + 4-mbit sram -- 28F3204C3 n flash memory plus sram ? reduces board design complexity n stacked die, chip scale package ? smallest possible memory subsystem footprint ? 16-mbit flash + 2-mbit sram: 8 mm by 10 mm area, 1.4 mm height ? 32-mbit flash + 4-mbit sram: 8 mm by 12 mm area, 1.4 mm height n industry compatibility ? sourcing flexibility n advanced sram technology ? 70 ns access time ? low power consumption with 30 ma read and 0.5 m a standby current n flash data integrator (fdi) software support ? real-time data storage and code execution from the same device ? no constraints on code/data partition size ? full flash file manager capability n 3 volt advanced+ boot block flash memory ? 90 ns 16-mb access time at 2.7 v ? 100 ns 32-mb access time at 2.7 v ? low power consumption with 9 ma read and 10 m a standby current ? improved 12 v production programming ? optimized block sizes for code+data storage with 8-kbyte parameter and 64-kbyte main blocks ? ultra fast program and erase suspend for code+data storage in real-time applications ? flexible, instantaneous individual block locking ? 128-bit flexible protection register ? minimum 100,000 erase cycles per block ? manufactured on 0.25 m etox? vi flash technology with a path to 0.18 m process n extended temperature operation ? ?40 c to +85 c the 3 volt advanced+ stacked chip scale package (stacked-csp) memory delivers a feature-rich solution for low-power applications. stacked-csp memory devices incorporate flash memory and static ram in one package with low voltage capability to achieve the smallest system memory solution form-factor t ogether with high-speed, low-power operations. the flash memory offers a protection register and flexible block locking to enable next generation security capability. combined with the intel-developed flash data integrator (fdi) software, the stacked-csp memory provides you with a cost-effective, flexible, code plus data storage solution. 3 volt advanced+ stacked chip scale package memory
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f1602c3 and 28F3204C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation, 1999 *other brands and names are the property of their respective owners.
e 28f1602c3, 28F3204C3 3 product preview contents page page 1.0 introduction..............................................5 1.1 product overview .........................................5 2.0 package ballouts...................................6 3.0 stacked chip scale package organization ............................................8 4.0 principles of operation .......................8 4.1 bus operation ..............................................9 5.0 flash memory modes of operation 11 5.1 read array .................................................11 5.2 read configuration ....................................11 5.3 read status register .................................12 5.4 read query................................................12 5.5 program mode ...........................................12 5.6 erase mode................................................13 6.0 flash memory flexible block locking .....................................................16 6.1 locking operation ......................................16 6.2 locked state ..............................................16 6.3 unlocked state...........................................16 6.4 lock-down state ........................................16 6.5 reading a blocks lock status ...................17 6.6 locking operation during erase suspend..17 6.7 status register error checking ..................17 7.0 flash memory 128-bit protection register ...................................................17 7.1 reading the protection register.................18 7.2 programming the protection register.........18 7.3 locking the protection register..................19 8.0 flash memory program and erase voltages ..................................................19 8.1 improved 12 volt production programming 19 8.2 f-v pp v pplk for complete protection ......19 9.0 electrical specifications..................20 9.1 absolute maximum ratings........................20 9.2 operating conditions..................................20 9.3 capacitance ...............................................21 9.4 dc characteristics .....................................21 9.5 flash ac characteristicsread operationsextended temperature .........25 9.6 flash ac characteristicswrite operationsextended temperature .........28 9.7 flash erase and program timings .............29 9.8 flash reset operations..............................31 9.9 sram ac characteristicsread operationsextended temperature .........32 9.10 sram ac characteristicswrite operationsextended temperature .........34 9.11 sram data retention characteristics extended temperature..............................35 10.0 migration guide information ..........36 11.0 system design considerations.......36 11.1 background ..............................................36 11.2 flash control considerations ...................37 11.3 noise reduction .......................................38 11.4 simultaneous operation ...........................39 11.5 printed circuit board notes ......................40 11.6 system design notes summary ...............40 12.0 ordering information......................41 13.0 additional information ...................41 appendix a: program/erase flowcharts ..........42 appendix b: cfi query structure .....................47 appendix c: word-wide memory map diagrams......................................................55 appendix d: device id table.............................57 appendix e: protection register addressing ..58 appendix f: mechanical specification .............59 appendix g: media information ........................61
28f1602c3, 28F3204C3 e 4 product preview revision history date of revision version description 03/30/1999 -001 original version 04/26/99 -002 corrected title headings in appendix b removed reference to 8-mbit devices, appendix b, table b7, device geometry definition corrected 4-mb sram i cc2 specification 06/15/99 -003 removed extra sram standby mode clarified operating mode table (section 4.1.2) clarified locking operations flowchart (appendix a)
e 28f1602c3, 28F3204C3 5 product preview 1.0 introduction this document contains the specifications for the 3 volt advanced+ stacked chip scale package (stacked-csp) memory. these memories are stacked memory solutions with 32-mb flash memory and 4-mb sram or 16-mb flash memory and 2-mb sram. throughout this document, the term 2.7 v refers to the full voltage range 2.7 vC3.3 v (except where noted otherwise) and f-v pp = 12 v refers to 12 v 5%. 1.1 product overview the intel ? stacked-csp memory provides secure low-voltage memory solutions for portable applications. this memory family combines two memory technologies, flash memory and sram, in one package. the flash memory delivers enhanced security features, a block locking capability that allows instant locking/unlocking of any flash block with zero-latency, and a 128-bit protection register that enable unique device identification, to meet the needs of next generation portable applications. discrete supply balls provide single voltage read, program, and erase capability at 2.7 v while also allowing 12 v f-v pp for faster production flash programming. the improved 12 v production programming feature reduce external logic and simplifies board designs when combining 12 v production programming with 2.7 v in-field programming capability. the 3 volt advanced+ stacked-csp memory products are available in the following densities: 16-mbit flash memories organized as 1024 kwords of 16 bits each with 2-mbit sram memories organized as 128kwords of 16 bits each. 32-mbit flash memories organized as 2048 kwords of 16 bits each with 4-mbit sram memories organized as 256-kwords of 16 bits each. the flash has eight 8-kb parameter blocks located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. the remaining flash memory is grouped into 64-kbyte main blo cks. all flash blocks can be locked or unlocked instantly to provide complete protection for code or data (see section 6.0 for details). the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. the flashs internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. the flashs status register indicates the status of the wsm by signifying block erase or word program completion and status. flash program and erase automation allows program and erase operations to be executed using an industry-standard two-write command sequence to the cui. program operations are performed in word increments. erase operations erase all locations within a block simultaneously. both program and erase operations can be suspended by the system software in order to r ead from any other flash block. in addition, data can be programmed to another flash block during an erase suspend. the 3 volt advanced+ stacked-csp memories offer two low-power savings features: automatic power savings (aps) for flash memory and standby mode for flash and sram. the device automatically enters aps mode following the completion of a read cycle from the flash memory. standby mode is initiated when the system deselects the device by driving f-ce# and s-cs 1 # or s-cs 2 inactive. power savings features significantly reduce power consumption. the flash memory can be reset by lowering f-rp# to gnd. this provides cpu-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/down sequences.
28f1602c3, 28F3204C3 e 6 product preview for complete current and voltage specifications, refer to section 9. 2.0 package ballouts this section provides device ball descriptions and package ballouts for the 3 volt advanced+ stacked- csp memory, which is available in a 72-ball (figure 1) package. this family of products provides upgrade paths up to 32-mbit flash memory with 4-mbit static ram density. 1 2 3 4 5 6 7 8 a b c d e f g h du du a 20 a 11 a 15 a 14 a 13 a 12 a 16 a 8 a 10 a 9 dq 15 s-we# f-we# du a 21 dq 13 dq 6 s-gnd f-wp# v pp a 19 dq 11 dq 10 s-lb#s-ub# s-oe# dq 9 dq 8 a 18 a 17 a 7 a 6 a 3 a 2 du du du a 5 a 4 a 0 f-ce# f-gnd f-rp# a 22 dq 12 s-cs 2 9 10 11 12 f-gnddududu d 14 dq 7 dq 4 dq 5 dq 2 dq 3 dq 0 dq 1 a 1 s-cs 1 # f-oe#dududu s-v cc f-v cc 12 11 10 9 8 7 6 5 a b c d e f g h du du du f-gnd a 12 a 13 a 14 a 15 dq 7 dq 14 s-we# dq 15 a 9 a 10 dq 5 dq 4 dq 6 dq 13 a 21 f-v cc dq 3 dq 2 dq 10 dq 11 a 19 dq 1 dq 0 dq 8 dq 9 s-oe# s-cs 1 #a 1 a 2 a 3 a 6 a 7 du du du f-oe# f-gnd f-ce# a 0 a 4 s-v cc s-cs 2 dq 12 a 22 4 3 2 1 a 11 a 20 du du a 8 a 16 du f-we# v pp f-wp# s-ub# s-lb# a 17 a 18 a 5 du du du f-rp# s-gnd top view, balls down bottom view, balls up note: 1. the upper address line, a 20 , for the 32-mbit flash with 4-mbit sram device is defined. flash upgrade address lines are also shown for a 21 ( 64-mbit flash) and a 22 ( 128-mbit flash) as well. in both the 32-mbit flash with 4-mbit sram and the 16-mbit flash with 2-mbit sram; 66 balls are populated (a 21 and a 22 are not populated). figure 1. 72-ball stacked chip scale package
e 28f1602c3, 28F3204C3 7 product preview table 1. 3 volt advanced+ stacked-csp ball descriptions symbol type name and function a 0 Ca 20 input address inputs for memory addresses. addresses are internally latched during a program or erase cycle. flash: 16-mbit x 16, a[0-19]; 32-mbit x 16, a[0-20] sram: 2-mbit x 16, a[0-16]; 4-mbit x 16, a[0-17] dq 0 C dq 15 input / output data inputs/outputs: inputs array data for sram write operations and on the second f-ce# and f-we# cycle during a flash program command. inputs commands to the flashs command user interface when f-ce# and f-we# are active. data is internally latched. outputs array, configuration and status register data. the data balls float to tri-state when the chip is de-selected or the outputs are disabled. f-ce# input flash chip enable: activates the flash internal control logic, input buffers, decoders and sense amplifiers. f-ce# is active low. f-ce# high de-selects the flash memory device and reduces power consumption to standby levels. s-cs 1 # input sram chip select1: activates the sram internal control logic, input buffers, decoders and sense amplifiers. s-cs 1 # is active low. s-cs 1 # high de-selects the sram memory device and reduces power consumption to standby levels. s-cs 2 input sram chip select2: activates the sram internal control logic, input buffers, decoders and sense amplifiers. s-cs 2 is active high. s-cs 2 low de-selects the sram memory device and reduces power consumption to standby levels. f-oe# input flash output enable: enables flashs outputs through the data buffers during a read operation. f-oe# is active low. s-oe# input sram output enable: enables srams outputs through the data buffers during a read operation. s-oe# is active low. f-we# input flash write enable: controls writes to flashs command register and memory array. f-we# is active low. addresses and data are latched on the rising edge of the second f-we# pulse. s-we# input sram write enable: controls writes to the sram memory array. s-we# is active low. s-ub# input sram upper byte enable: enable the upper bytes for sram (dq 8 Cdq 15 ). s-ub# is active low. s-lb# input sram lower byte enable: enable the lower bytes for sram (dq 0 Cdq 7 ). s-lb# is active low. f-rp# input flash reset/deep power-down: uses two voltage levels (v il , v ih ) to control reset/deep power-down mode. when f-rp# is at logic low, the device is in reset/deep power-down mode , which drives the outputs to high-z, resets the write state machine, and minimizes current levels (i ccd ). when f-rp# is at logic high, the device is in standard operation . when f-rp# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
28f1602c3, 28F3204C3 e 8 product preview table 1. 3 volt advanced+ stacked-csp ball descriptions (continued) symbol type name and function f-wp# input flash write protect: controls the lock-down function of the flexible locking feature. when f-wp# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. when f-wp# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. after f-wp# goes low, any blocks previously marked lock-down revert to that state. see section 6.0 for details on block locking. f-v cc supply flash power supply: [2.7 v C3.3 v] supplies power for device operations. s-v cc supply sram power supply: [2.7 vC3.3 v] supplies power for device operations. f-v pp input / supply flash program/erase power supply: [1.65 vC3.3 v or 11.4 vC12.6 v] operates as a input at logic levels to control complete flash protection. supplies power for accelerated flash program and erase operations in 12 v 5% range. this ball cannot be left floating. lower f- v pp v pplk , to protect all contents against program and erase commands. set f- v pp = f- v cc for in-system read, program and erase operations . in this configuration, f-v pp can drop as low as 1.65 v to allow for resistor or diode drop from the system supply. note that if f-v pp is driven by a logic signal, v ih = 1.65 v. that is, f-v pp must remain above 1.65 v to perform in-system flash modifications. raise f- v pp to 12 v 5% for faster program and erase in a production environment. applying 12 v 5% to f-v pp can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. f-gnd supply flash ground: for all internal circuitry. all ground inputs must be connected. s-gnd supply sram ground: for all internal circuitry. all ground inputs must be connected. du dont use: do not drive ball to v ih or v il . leave unconnected. 3.0 stacked chip scale package organization the 3 volt advanced+ stacked-csp contains a flash and a sram component. the flash device is asymmetrically-blocked to enable system integration of code and data storage in a single device. each flash block can be erased independently of the others up to 100,000 times. for the address locations of each flash block, see the memory maps in appendix c. figure 2 illustrates the stacked-csp block diagram. 4.0 principles of operation the 3 volt advanced+ stacked-csp incorporates flash and sram in a single package. the flash memory utilizes a cui and automated algorithms to simplify program and erase operations. the internal algorithms are controlled by an internal wsm. the cui handles the interface to the data and address latches, as well as system status requests during wsm operation.
e 28f1602c3, 28F3204C3 9 product preview 1,048,576 x16 bit (16 mbit) 2,097,152 x16 bit (32 mbit) 3 volt advanced+ boot block flash memory 131,072 x16 bit (2 mbit) 262,144 x16 bit (4 mbit) sram f-ce# f-oe# f-we# f-rp# f-wp# a 17-19 /a 18-20 a 0-16 /a 0-17 s-cs 1 # s-cs 2 s-oe# s-we# s-ub# s-lb# dq 0-15 s-v cc s-gnd f-v pp f-v cc f-gnd figure 2. 3 volt advanced+ stacked chip scale package block diagram 4.1 bus operation the 3 volt advanced+ stacked-csp memory devices read, program and erase in - system via the local cpu or microcontroller. all bus cycles to or from the stacked-csp conform to standard microcontroller bus cycles. four control balls dictate the data flow in and out of the flash component: f-ce#, f-oe#, f-we# and f-rp#. four control balls handle the data flow in and out of the sram component: s-cs 1 #, s-cs 2 , s-oe#, and s-we# these bus operations are summarized in tables 2 and 3. 4.1.1 read the sram has one read mode while the flash memory has four read modes: read array, read configuration, read status and read query. these flash memory read modes are accessible independent of the f-v pp voltage. the appropriate read mode command must be issued to the flash memory to enter the corresponding mode. upon initial device power - up or after exit from reset, the flash device automatically defaults to read array mode. f-ce# and f-oe# must be driven active to obtain data from the flash component. at the outputs. s-cs 1 #, s-cs 2 , and s-oe# must be driven active to obtain data from the sram device. for all reads operations, f-we#, s-we# and f-rp# must be at v ih . figure 6 illustrates a flash read cycle. 4.1.2 output disable with f-oe# and s-oe# inactive, the stacked-csp outputs are disabled. output balls are placed in a high - impedance state.
28f1602c3, 28F3204C3 e 10 product preview table 2. flash operating mode (1) mode note f-rp# f-ce# f-oe# f-we# dq 0-15 flash read 2,3 v ih v il v il v ih d out flash output disable 2 v ih v il v ih v ih high z flash write 4 v ih v il v ih v il d in flash standby 2 v ih v ih x x high z flash reset 2,5 v il x x x high z sram read 2 x v ih x x high z sram output disable 2 x v ih x x high z sram write 2 x v ih x x high z notes: 1. f-ce# and s-cs 1 # and s-cs 2 should not be asserted at the same time. flash device cannot be accessed while sram is in data retention mode. 2. x must be v il , v ih for control balls and addresses. 3. see dc characteristics for v pplk , v pp1 , v pp2 , v pp3 , voltages. 4. table 5 describes valid input data (d in ) during a flash command sequence. 5. f-rp# must be at gnd 0.2 v to meet the maximum deep power-down current specified. table 3. sram operating mode (1) mode note s-cs 1 # s-cs 2 s-oe# s-we# s-ub# s-lb# dq 0-15 flash read 2,3,5 v ih v il xxxx high z flash output disable 2,5 v ih v il xxxx high z flash write 4 v ih v il v ih v il x x high z flash standby 2,5 v ih xxxxx high z sram read 2 v il v ih v il v ih xxd out sram output disable 2 v il v ih v ih v ih x x high z sram write 2 v il v ih v ih v il xxd in sram standby 2 v ih xxxxx high z sram standby 2 x v il xxxx high z sram standby 2 x x x x v ih v ih high z notes: 1. f-ce# and s-cs 1 # and s-cs 2 should not be asserted at the same time. flash device cannot be accessed while sram is in data retention mode. 2. x must be v il , v ih for control balls and addresses. 3. see dc characteristics for v pplk , v pp1 , v pp2 , v pp3 , voltages. 4. table 5 describes valid input data (d in ) during a flash command sequence. 5. sram can be placed in standby by asserting s-cs 1 # to v ih or s-cs 2 to v il .
e 28f1602c3, 28F3204C3 11 product preview 4.1.3 standby with f-ce# and s-sc 1 # or s-sc 2 inactive, the stacked-csp enters a standby mode, which substantially reduces device power consumption. in standby, outputs are placed in a high-impedance state independent of f-oe# and s-oe#. if the flash is deselected during a program or erase operation, the flash continues to consume active power until the program or erase operation is complete. 4.1.4 reset the flash memory supports a reset signal, f-rp. from read mode, f-rp# at v il for time t plph deselects the memory, places output drivers in a high - impedance state, and turns off all internal circuits. after return from reset, a time t phqv is required until the initial read access outputs are valid. a delay (t phwl or t phel ) is required after return from reset before a write can be initiated. after this wake - up interval, normal operation is restored. the flash device resets to read array mode, the status register is set to 80h, and all blocks are locked. this case is shown in figure 8a. if f-rp# is taken low for time t plph during a flash program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. the abort process goes through the following sequence: when f-rp# goes low, the device shuts down the operation in progress, a process which takes time t plrh to complete. after this time t plrh , the part will either reset to read array mode (if f-rp# has gone high during t plrh , figure 8b) or enter reset mode (if f-rp# is still logic low after t plrh , figure 8c). in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl /t phel must be waited before a read or write operation is initiated, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when f-rp# goes high. as with any automated device, it is important to assert f-rp# during system reset. when the system comes out of reset, processor expects to read from the flash memory. automated flash memories provide status information when read during program or block erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intel ? flash memories allow proper cpu initialization following a system reset through the use of the f-rp# input. in this application, f-rp# is controlled by the same reset# signal that resets the system cpu. 4.1.5 write writes to flash take place when both f-ce# and f-we# are low and f-oe# is high. writes to sram take place when both s-cs 1 # and s-we# are low and s-oe# and s-sc 2 are high. commands are written to the flash memorys command user interface (cui) using standard microprocessor write timings to control flash operations. the cui does not occupy an addressable memory location within the flash component. the address and data buses are latched on the rising edge of the second f-we# or f-ce# pulse, whichever occurs first. figure 7 illustrates a program and erase operation. the available commands are shown in table 5. 5.0 flash memory modes of operation the flash memory has four read modes: read array, read configuration, read status, and read query. the write modes are program and erase. three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. these modes are reached using the commands summarized in table 5. 5.1 read array when f-rp# transitions from v il (reset) to v ih , the device defaults to read array mode and will respond to the read control inputs without any additional cui commands. in addition, the address of the desired location must be applied to the address balls. if the device is not in read array mode, as would be the case after a program or erase operation, the read array command (ffh) must be written to the cui before array reads can take place. 5.2 read configuration the read configuration mode outputs the manufacturer/device identifier. the device is switched to this mode by writing the read configuration command (90h). once in this mode,
28f1602c3, 28F3204C3 e 12 product preview read cycles from addresses shown in table 4 retrieve the specified information. to return to read array mode, write the read array command (ffh). the read configuration mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in table 4 retrieve the specified information. to return to read array mode, write the read array command (ffh). table 4. read configuration table item address data manufacturer code (x16) 00000 0089 device id (see appendix g) 00001 id block lock configuration 2 xx002 (1) lock block is unlocked dq 0 = 0 block is locked dq 0 = 1 block is locked-down dq 1 = 1 protection register lock 3 80 pr-lk protection register (x16) 81-88 pr notes: 1. xx specifies the block address of lock configuration being read. 2. see section 6.4 for valid lock status outputs. 3. see section 7.0 for protection register information. 4. other locations within the configuration address space are reserved by intel for future use. 5.3 read status register the status register indicates the status of device operations, and the success/failure of that operation. the read status register (70h) command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the array, issue a read array (ffh) command. the status register bits are output on dq 0 Cdq 7 . the upper byte, dq 8 Cdq 15 , outputs 00h during a read status register command. the contents of the status register are latched on the falling edge of f-oe# or f-ce#, whichever occurs last. this prevents possible bus errors which might occur if status register contents change while being read. f-ce# or f-oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, sr.7 will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the desired operation (see table 6). 5.3.1 clearing the status register the wsm sets status bits 1 through 7 to 1, and clears bits 2, 6 and 7 to 0, but cannot clear status bits 1 or 3 through 5 to 0. because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the use of the clear status register (50h) command. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in s equence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note that the read array command must be issued before data can be read from the memory array. resetting the device also clears the status register. 5.4 read query the read query mode outputs common flash interface (cfi) data when the device is read. this can be accessed by writing the read query command (98h). the cfi data structure contains information such as block size, density, command set and electrical specifications. once in this mode, read cycles from addresses shown in appendix b retrieve the specified information. to return to read array mode, write the read array command (ffh). 5.5 program mode programming is executed using a two - write sequence. the program setup command (40h) is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. programming the memory results in specific bits within an address location
e 28f1602c3, 28F3204C3 13 product preview being changed to a 0. if the user attempts to program 1s, the memory cell contents do not change and no error occurs. the status register indicates programming status: while the program sequence executes, status bit 7 is 0. the status register can be polled by toggling either f-ce# or f-oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit sr.4 of the status register is set to indicate a program failure. if sr.3 is set then f-v pp was not within acceptable limits, and the wsm did not execute the program command. if sr.1 is set, a program operation was attempted on a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read array mode. 5.5.1 suspending and resuming program the program suspend command halts an in - progress program operation so that data can be read from other locations of memory. once the programming process starts, writing the program suspend command to the cui requests that the wsm suspend the program sequence (at predetermined points in the program algorithm). the device continues to output status register data after the program suspend command is written. polling status register bits sr.7 and sr.2 will determine when the program operation has been suspended (both will be set to 1). t whrh1 /t ehrh1 specify the program suspend latency. a read array command can now be written to the cui to read data from blo cks other t han that which is suspended. the only other valid commands, while program is suspended, are read status register, read configuration, read query, and program resume. after the program resume command is written to the flash memory, the wsm will continue with the programming process and status register bits sr.2 and sr.7 will automatically be cleared. the device automatically outputs status register data when read (see figure 16 in appendix a, program suspend/resume flowchart ) after the program resume command is written. f-v pp must remain at the same f-v pp level used for program while in program suspend mode. f-rp# must also remain at v ih . 5.6 erase mode to erase a block, write the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. only one block can be erased at a time. the wsm will execute a sequence of internally timed events to program all bits within the block to 0, erase all bits within the block to 1, then verify that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is a 0. when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr.5 of the status register will be set to a 1, indicating an erase failure. if f-v pp was not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr.5 of the status register is set to indicate an erase error, and sr.3 is set to a 1 to identify that f-v pp supply voltage was not within acceptable limits. after an erase operation, clear the status register (50h) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. 5.6.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase - sequence interruption in order to read data from or program data to another block in memory. once the erase sequence is started, writing the erase suspend command to the cui suspends the erase sequence at a predetermined point in the erase algorithm. the status register will indicate if/when the erase operation has been suspended. erase suspend latency is specified by t whrh2 /t ehrh2 .
28f1602c3, 28F3204C3 e 14 product preview a read array/program command can now be written to the cui to read/program data from/to blocks other t han that which is suspended. this nested program command can subsequently be suspended to read yet another location. the only valid commands while erase is suspended are read status register, read configuration, read query, program setup, program resume, erase resume, lock block, unlock block and lock-down block. during erase suspend mode, the chip can be placed in a pseudo - standby mode by taking f-ce# to v ih . this reduces active current consumption. erase resume continues the erase sequence when f-ce# = v il . as with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. table 5. flash memory command bus definitions first bus cycle second bus cycle command notes oper addr data oper addr data read array 4 write x ffh read configuration 2, 4 write x 90h read ia id read query 2, 4 write x 98h read qa qd read status register 4 write x 70h read x srd clear status register 4 write x 50h program 3,4 write x 40h/10h write pa pd block erase/confirm 4 write x 20h write ba d0h program/erase suspend 4 write x b0h program/erase resume 4 write x d0h lock block 4 write x 60h write ba 01h unlock block 4 write x 60h write ba d0h lock-down block 4 write x 60h write ba 2fh protection program 4 write x c0h write pa pd x = dont care pa = prog addr ba = block addr ia = identifier addr. qa = query addr. srd = status reg. data pd = prog data id = identifier data qd = query data notes: 1. bus operations are defined in table 2. 2. following the read configuration or read query commands, read operations output device configuration or cfi query information, respectively. 3. either 40h or 10h command is valid, but the intel standard is 40h. 4. when writing commands, the upper data bus [dq8 Cdq15] should be either v il or v ih , to minimize current draw.
e 28f1602c3, 28F3204C3 15 product preview table 6. flash memory register bit definition wsms ess es ps vpps pss bls r 76543210 notes: sr.7 write state machine status 1 = ready (wsms) 0 = busy check write state machine bit first to determine word program or block erase completion, before checking program or erase status bits. sr.6 = erase - suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erase 0 = successful block erase when this bit is set to 1, wsm has applied the max. number of erase pulses and is still unable to verify successful block erasure. sr.4 = program status (ps) 1 = error in programming 0 = successful programming when this bit is set to 1, wsm has attempted but failed to program a word/byte. sr.3 = f-v pp status (vpps) 1 = f-v pp low detect, operation abort 0 = f-v pp ok the f-v pp status bit does not provide continuous indication of v pp level. the wsm interrogates f-v pp level only after the program or erase command sequences have been entered, and informs the system if f-v pp has not been switched on. the f-v pp is also checked before the operation is verified by the wsm. the f-v pp status bit is not guaranteed to report accurate feedback between v pplk and v pp1 min. sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to 1. pss bit remains set to 1 until a program resume command is issued. sr.1 = block lock status 1 = prog/erase attempted on a locked block; operation aborted. 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr.0 = reserved for future enhancements (r) this bit is reserved for future use and should be masked out when polling the status register. note: 1. a command sequence error is indicated when both sr.4, sr.5 and sr.7 are set.
28f1602c3, 28F3204C3 e 16 product preview 6.0 flash memory flexible block locking the intel 3 volt advanced+ stacked-csp products offer an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. this locking scheme offers two levels of protection. the first level allows software-only control of block locking (useful for data blocks that c hange frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). the following sections will discuss the operation of the locking system. the term state [xyz] will be used to specify locking states; e.g., state [001], where x = value of wp#, y = bit dq 1 of the block lock status register, and z = bit dq 0 of the block lock status register. table 8 defines all of these possible locking states. 6.1 locking operation the following concisely summarizes the locking functionality. all blocks power-up locked, t hen can be unlocked or locked with the unlock and lock commands. the lock-down command lo cks a block and prevents it from being unlocked when wp# = 0. ? when wp# = 1, lock-down is overridden and commands can unlock/lock locked- down blocks. ? when wp# returns to 0, locked-down blocks return to lock-down. ? lock-down is cleared only when the device is reset or powered-down. the locking status of each block can set to locked, unlocked, and lock-down, each of which will be described in the following sections. a comprehensive state table for the locking functions is shown in table 8, and a flowchart for locking operations is shown in figure 19. 6.2 locked state the default status of all blocks upon power-up or reset is locked (states [001] or [101]). locked blocks are fully protected from alteration. any program or erase operations attempted on a locked block will return an error on bit sr.1 of the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. an unlocked block can be locked by writing the lock command sequence, 60h followed by 01h. 6.3 unlocked state unlocked blocks (states [ 000], [100], [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by writing the unlock command sequence, 60h followed by d0h. 6.4 lock-down state blocks that are locked-down (state [ 011]) are protected from program and erase operations (just like locked blocks), but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked- down by writing the lock-down command sequence, 60h followed by 2fh. locked-down blocks revert to the locked state w hen the device is reset or powered down. the lock-down function is dependent on the wp# input ball. when wp# = 0, blo cks in lock-down [011] are protected from program, erase, and lock status changes. when wp# = 1, the lock-down function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. these blocks can t hen be re-locked [111] and unlocked [110] as desired while wp# remains high. when wp# goes low, blo cks that were previously locked-down return to the lock-down state [011] regardless of any changes made while wp# was high. device reset or power- down resets all blocks, including those in lock- down, to locked state.
e 28f1602c3, 28F3204C3 17 product preview 6.5 reading a blocks lock status the lock status of every block can be read in the configuration read mode of the device. to enter this mode, write 90h to the device. subsequent reads at block address + 00002 will output the lock status of that block. the lock status is represented by the lowest two output balls, dq 0 and dq 1 . dq 0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock-down. dq 1 indicates lock-down status and is set by the lock-down command. it cannot be cleared by software, only by device reset or power- down. table 7. block lock status item address data block lock configuration xx002 lock block is unlocked dq 0 = 0 block is locked dq 0 = 1 block is locked-down dq 1 = 1 6.6 locking operation during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command (b0h), then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after completing any desired lock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. 6.7 status register error checking using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. since locking changes are performed using a two cycle comm and sequence, e.g., 60h followed by 01h to lock a block, following the configuration setup command (60h) with an invalid command will produce a lock command error (sr.4 and sr.5 will be set to 1) in the status register. if a lock command error occurs during an erase suspend, sr.4 and sr.5 will be set to 1, and will remain at 1 after the erase is resumed. when erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. a similar situation happens if an error occurs during a program operation error nested within an erase suspend. 7.0 flash memory 128-bit protection register the 3 volt advanced+ stacked-csp architecture includes a 128-bit protection register than can be used to increase the security of a system design. for example, the number contained in the protection register can be used to mate the flash component with other system com ponents such as the cpu or asic, preventing device substitution. the 128-bits of the protection register are divided into two 64-bit segments. one of the segments is programmed at the intel factory with a unique 64-bit number, which is unchangeable. the other segment is left blank for customer designs to program as desired. once the customer segment is programmed, it can be locked to prevent reprogramming.
28f1602c3, 28F3204C3 e 18 product preview table 8. block locking state transitions current state erase/prog lock command input result [next state] wp# dq 1 dq 0 name allowed? lock unlock lock-down 000 unlocked yes goes to [001] no change goes to [011] 0 0 1 locked (default) no no change goes to [000] goes to [011] 0 1 1 locked- down no no change no change no change 1 0 0 unlocked yes goes to [101] no change goes to [111] 1 0 1 locked no no change goes to [100] goes to [111] 1 1 0 lock-down disabled yes goes to [111] no change goes to [111] 1 1 1 lock-down disabled no no change goes to [110] no change notes: 1. in this table, the notation [xyz] denotes the locking state of a block, where x = wp#, y = dq 1 , and z = dq 0 . the current locking state of a block is defined by the state of wp# and the two bits of the block lock status (dq 0 , dq 1 ). dq 0 indicates if a block is locked (1) or unlocked (0). dq 1 indicates if a block has been locked-down (1) or not (0). 2. at power-up or device reset, all blocks default to locked state [001] (if wp# = 0). holding wp# = 0 is the recommended default. 3. the erase/program allowed? column shows whether erase and program operations are enabled (yes) or disabled (no) in that blocks current locking state. 4. the lock command input result [next state] column shows the result of writing the three locking commands (lock, unlock, lock-down) in the current locking state. for example, goes to [001] would mean that writing the command to a block in the current locking state would change it to [001]. 7.1 reading the protection register the protection register is read in the configuration read mode. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in appendix e retrieve the specified information. to return to read array mode, write the read array command (ffh). 7.2 programming the protection register the protection register bits are programmed using the two-cycle protection program comm and. the 64-bit number is programmed 16 bits at a time for word-wide parts. first write the protection program setup command, c0h. the next write to the device will latch in address and data and program the specified location. the allowable addresses are shown in appendix e. see figure 20 for the protection register programming flowchart . any attempt to address protection program commands outside the defined protection register address space will result in a status register error (program error bit sr.4 will be set to 1). attempting to program or to a previously locked protection register segment will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1).
e 28f1602c3, 28F3204C3 19 product preview 7.3 locking the protection register the user-programmable segment of the protection register is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the intel factory to protect the unique device number. this bit is set using the protection program command to program fffd to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). protection register lockout state is not reversible. 4 words factory programmed 4 words user programmed pr-lock 88h 85h 84h 81h 80h 0645_05 figure 3. protection register memory map 8.0 flash memory program and erase voltages intel 3 volt advanced+ stacked-csp products provide in-system programming and erase in the 1.65 vC3.3 v range. for fast production programming, it also includes a low-cost, backward- compatible 12 v programming feature. 8.1 improved 12 volt production programming when f-v pp is between 1.65 v and 3.3 v, all program and erase current is drawn through the f-v cc signal. note that if f-v pp is driven by a logic signal, v ih min = 1.65 v. that is, f-v pp must remain above 1.65 v to perform in- system flash modifications. when f-v pp is connected to a 12 v power supply, the device draws program and erase current directly from the f-v pp signal. this eliminates the need for an external switching transistor to control the voltage f-v pp . figure 12 shows examples of how the flash power supplies can be configured for various usage models. the 12 v f-v pp mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to f-v pp during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 8.2 f-v pp v pplk for complete protection in addition to the flexible block locking, the f-v pp programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. when f-v pp is below v pplk , any program or erase operation will result in a error, prompting the corresponding status register bit (sr.3) to be set.
28f1602c3, 28F3204C3 e 20 product preview 9.0 electrical specifications 9.1 absolute maximum ratings* extended operating temperature during read .......................... C40 c to +85 c during flash block erase and program.......................... C40 c to +85 c temperature under bias........ C40 c to +85 c storage temperature................. C65 c to +125 c voltage on any ball (except f-v cc /s-v cc and f-v pp ) with respect to gnd ............. C0.5 v to +3.3 v 1 f-v pp voltage (for block erase and program) with respect to gnd .......C0.5 v to +13.5 v 1,2,4 f-v cc /s-v cc supply voltage with respect to gnd ............. C0.2 v to +3.3 v 1 output short circuit current...................... 100 ma 3 notice: this datasheet contains preliminary information on new products in the design phase of production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc voltage is C0.5 v on input/output balls. during transitions, this level may undershoot to C2.0 v for periods < 20 ns. maximum dc voltage on input/output balls is f-v cc /s-v cc + 0.5 v which, during transitions, may overshoot to f-v cc /s-v cc + 2.0 v for periods < 20 ns. 2. maximum dc voltage on f-v pp may overshoot to +14.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. f-v pp voltage is normally 1.65 vC3.3 v. connection to supply of 11.4 vC12.6 v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. f-v pp may be connected to 12 v for a total of 80 hours maximum. see section 8.0 for details. 9.2 operating conditions table 9. temperature and voltage operating conditions symbol parameter notes min max units t a operating temperature C40 +85 c v cc1 f-v cc /s-v cc supply voltage 1 2.7 3.3 volts v cc2 1 3.0 3.3 v pp1 supply voltage 1 1.65 3.3 volts v pp2 1, 2 11.4 12.6 volts cycling block erase cycling 2 100,000 cycles notes: 1. f-v cc /s-v cc must share the same supply when they are in the v cc1 range. 2. applying f-v pp = 11.4 v C12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. see section 8.1 for details .
e 28f1602c3, 28F3204C3 21 product preview 9.3 capacitance t a = 25 c, f = 1 mhz sym parameter notes typ max units conditions c in input capacitance 1 16 18 pf v in = 0 v c out output capacitance 1 20 22 pf v out = 0 v note: 1. sampled, not 100% tested. 9.4 dc characteristics 2.7 v C3.3 v sym parameter device note typ max unit test conditions i li input load current flash/sram 1,7 2 a f-v cc /s-v cc = v cc1 max v in = v cc1 max or gnd i lo output leakage current flash/ sram 1,7 0.2 10 a f-v cc /s-v cc = v cc1 max v in = v cc1 max or gnd i ccs v cc standby current flash 1 10 25 a f-v cc = v cc1 max f-ce# = f-rp# = v cc1 f-wp# = v cc1 or gnd v in = v cc1 max or gnd 2-mb sram 1 0.5 10 a s-v cc = v cc1 max s-cs# 1 = v cc , s-cs 2 = v cc or 4-mb sram 1 0.5 20 a s-cs 2 = gnd v in = v cc1 max or gnd i ccd v cc deep power- down current flash 1,7 7 20 a f-v cc = v cc max v in = v cc1 max or gnd f-rp# = gnd 0.2 v i cc operating power supply current (cycle time = 1 m s) 2-mb sram 1 3 7 ma i io = 0 ma, s-cs# 1 = v il s-cs 2 = s-we# = v ih v in = v il or v ih 4-mb sram 1 8 10 ma i cc2 operating power supply current (min cycle time) 2-mb sram 1 30 40 ma cycle time = min, 100% duty, i io = 0 ma, s-cs# 1 = v il , s-cs 2 = v ih , v in = v il or v ih 4-mb sram 1 30 45 ma i ccr v cc read current flash 1,5, 7 918ma f-v cc = v cc1 max f-oe# = v ih , f-ce# = v il f = 5 mhz, i out = 0 ma v in = v il or v ih
28f1602c3, 28F3204C3 e 22 product preview 9.4 dc characteristics (continued) 2.7 v C3.3 v sym parameter device note typ max unit test conditions i ccw v cc program current flash 1,4 18 55 ma f-v pp = v pp1 program in progress 815ma f-v pp = v pp2 (12 v) program in progress i cce v cc erase current flash 1,4 16 45 ma f-v pp = v pp1 erase in progress 815ma f-v pp = v pp2 (12 v) erase in progress i cces v cc erase suspend current flash 1,2,4 10 25 a f-ce# = v ih , erase suspend in progress i ccws v cc program suspend current flash 1,2,4 10 25 a f-ce# = v ih , program suspend in progress i ppd f-v pp deep power- down current flash 1 0.2 5 a f-rp# = gnd 0.2 v f-v pp v cc1 i pps f-v pp standby current flash 1 0.2 5 a f-v pp v cc1 i ppr f-v pp read current flash 1 2 15 a f-v pp v cc1 1,4 50 200 a f-v pp 3 v cc1 i ppw f-v pp program current flash 1,4 0.05 0.1 ma f-v pp =v pp1 program in progress 822ma f-v pp = v pp2 (12 v) program in progress i ppe f-v pp erase current flash 1,4 0.05 0.1 ma f-v pp = v pp1 program in progress 822ma f-v pp = v pp2 (12 v) program in progress i ppes f-v pp erase suspend current flash 1,4 0.2 5 a f-v pp = v pp1 erase suspend in progress 50 200 a f-v pp = v pp2 (12 v) erase suspend in progress i ppws f-v pp program suspend current flash 1,4 0.2 5 a f-v pp = v pp1 program suspend in progress 50 200 a f-v pp = v pp2 (12 v) program suspend in progress
e 28f1602c3, 28F3204C3 23 product preview 9.4 dc characteristics (continued) 2.7 v C3.3 v sym parameter device note min max unit test conditions v il input low voltage flash/ sram C0.4 v cc *0.22 v v ih input high voltage flash/ sram 2.2 v cc +0.3 v v ol output low voltage flash/ sram 7 C0.10 0.10 v f-v cc /s-v cc = v cc1 min i ol = 100 m a v oh output high voltage flash/ sram 7v cc C 0.1 v f-v cc /s-v cc = v cc1 min i oh = C100 m a v pplk f-v pp lock-out voltage flash 3 1.0 v complete write protection v pp1 f-v pp during program / erase flash 3 1.65 3.3 v v pp2 operations 3,6 11.4 12.6 v lko v cc prog/erase lock voltage flash 1.5 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal f-v cc /s-v cc , t a = +25 c. 2. i cces and i ccws are specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . if the device is read while in program suspend, current draw is the sum of i ccws and i ccr . 3. erase and program are inhibited when f-v pp < v pplk and not guaranteed outside the valid f-v pp ranges of v pp1 and v pp2 . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 6. applying f-v pp = 11.4 vC12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. see section 8.1 for details. 7. the test conditions f-v cc /s-v cc = v cc1 min refer to the maximum or minimum v cc1 or v cc2 voltage listed at the top of each column.
28f1602c3, 28F3204C3 e 24 product preview input output test points v cc 0.0 v cc 2 v cc 2 0645_07 figure 4. input/output reference waveform device under test out r 1 v ccq c l r 2 0645_08 figure 5. test configuration flash test configuration component values table test configuration c l (pf) r 1 ( w )r 2 ( w ) 2.7 v C3.3 v standard test 50 25k 25k note: c l includes jig capacitance.
e 28f1602c3, 28F3204C3 25 product preview 9.5 flash ac characteristics read operations (1, 4) extended temperature density 16 mbit product C90 C110 volt 3.0 vC3.3 v 2.7 vC3.3 v 3.0 vC3.3 v 2.7 vC3.3 v # sym parameter note min max min max min max min max unit r1 t avav read cycle time 80 90 100 110 ns r2 t avqv address to output delay 80 90 100 110 ns r3 t elqv f-ce# to output delay 2 80 90 100 110 ns r4 t glqv f-oe# to output delay 230303030ns r5 t phqv f-rp# to output delay 150 150 150 150 ns r6 t elqx f-ce# to output in low z 30 0 0 0 ns r7 t glqx f-oe# to output in low z 30 0 0 0 ns r8 t ehqz f-ce# to output in high z 320202020ns r9 t ghqz f-oe# to output in high z 320202020ns r10 t oh output hold from address, f-ce#, or f-oe# change, whichever occurs first 30 0 0 0 ns notes: 1. see figure 6 ac waveform: flash read operations . 2. f-oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 3. sampled, but not 100% tested. 4. see figure 4, input/output reference waveform for timing measurements and maximum allowable input slew rate.
28f1602c3, 28F3204C3 e 26 product preview 9.5 flash ac characteristics read operations (1, 4) extended temperature, (continued) density 32 mbit product C100 (5) C110 volt 3.0 vC3.3 v 2.7 vC3.3 v 3.0 vC3.3 v 2.7 vC3.3 v # sym parameter note min max min max min max min max unit r1 t avav read cycle time 90 100 100 110 ns r2 t avqv address to output delay 90 100 100 110 ns r3 t elqv f-ce# to output delay 2 90 100 100 110 ns r4 t glqv f-oe# to output delay 2 30303030ns r5 t phqv f-rp# to output delay 150 150 150 150 ns r6 t elqx f-ce# to output in low z 30 0 0 0 ns r7 t glqx f-oe# to output in low z 30 0 0 0 ns r8 t ehqz f-ce# to output in high z 3 20202020ns r9 t ghqz f-oe# to output in high z 3 20202020ns r10 t oh output hold from address, f-ce#, or f-oe# change, whichever occurs first 30 0 0 0 ns notes: 1. see figure 6 ac waveform: flash read operations. 2. f-oe# may be delayed up to t elqv Ct glqv after the falling edge of f-ce# without impact on t elqv . 3. sampled, but not 100% tested. 4. see figure 4, input/output reference waveform for timing measurements and maximum allowable input slew rate. 5. speed bin not initially available.
e 28f1602c3, 28F3204C3 27 product preview address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v high z valid output data valid standby high z r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 figure 6. ac waveform: flash read operations
28f1602c3, 28F3204C3 e 28 product preview 9.6 flash ac characteristics write operations (1, 5, 6) extended temperature density 16 mbit 32 mbit product C90 C110 C100 C110 3.0 v C 3.3 v 80 100 90 100 2.7 v C 3.3 v 90 110 100 110 # sym parameter note min min min min min min min min unit w1 t phwl / t phel f-rp# high recovery to f-we# (f-ce#) going low 150 150 150 150 150 150 150 150 ns w2 t elwl t wlel f-ce# (f-we#) setup to f-we# (f-ce#) going low 00000000ns w3 t eleh t wlwh f-we# (f-ce#) pulse width 4 5060707060707070 ns w4 t dvwh t dveh data setup to f-we# (f-ce#) going high 2 5050606050606060 ns w5 t avwh t aveh address setup to f-we# (f-ce#) going high 2 5060707060707070 ns w6 t wheh t ehwh f-ce# (f-we#) hold time from f-we# (f-ce#) high 00000000ns w7 t whdx t ehdx data hold time from f-we# (f-ce#) high 2 00000000ns w8 t whax t ehax address hold time from f-we# (f-ce#) high 2 00000000ns w9 t whwl t ehel f-we# (f-ce#) pulse width high 4 3030303030303030 ns w10 t vpwh t vpeh f-v pp setup to f-we# (f-ce#) going high 3 200 200 200 200 200 200 200 200 ns w11 t qvvl f-v pp hold from valid srd 3 00000000ns notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. refer to table 5 for valid a in or d in . 3. sampled, but not 100% tested. 4. write pulse width (t wp ) is defined from f-ce# or f-we# going low (whichever goes low last) to f-ce# or f-we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . similarly, write pulse width high (t wph ) is defined from f-ce# or f-we# going high (whichever goes high first) to f-ce# or f-we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl . 5. see figure 4, input/output reference waveform for timing measurements and maximum allowable input slew rate. 6. see figure 7, ac waveform: flash program and erase operations.
e 28f1602c3, 28F3204C3 29 product preview 9.7 flash erase and program timings (1) f-v pp 1.65 v C3.3 v 11.4 vC12.6 v symbol parameter note typ (1) max typ (1) max unit t bwpb 8-kb parameter block program time (byte) 2, 3 0.16 0.48 0.08 0.24 s 4-kw parameter block program time (word) 2, 3 0.10 0.30 0.03 0.12 s t bwmb 64-kb main block program time (byte) 2, 3 1.2 3.7 0.6 1.7 s 32-kw main block program time(word) 2, 3 0.8 2.4 0.24 1 s t whqv1 / t ehqv1 byte program time 2, 3 17 165 8 185 s word program time 2, 3 22 200 8 185 s t whqv2 / t ehqv2 8-kb parameter block erase time (byte) 2, 3 0.5 4 0.4 4 s 4-kw parameter block erase time (word) 2, 3 0.5 4 0.4 4 s t whqv3 / t ehqv3 64-kb main block erase time (byte) 2, 3 1 5 0.6 5 s 32-kw main block erase time (word) 2, 3 1 5 0.6 5 s t whrh1 / t ehrh1 program suspend latency 3 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 3 5 20 5 20 s notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes external system-level overhead. 3. sampled, but not 100% tested.
28f1602c3, 28F3204C3 e 30 product preview addresses [a] ce#(we#) [e(w)] oe# [g] we#(ce#) [w(e)] data [d/q] rp# [p] ih v il v ih v il v ih v il v ih v il v il v il v in d in a in a valid srd in d ih v high z ih v il v v [v] pp pph v pplk v pph v1 2 wp# il v ih v in d ab c d e f w8 w6 w9 w3 w4 w7 w1 w5 w2 w10 w11 (note 1) (note 1) notes: 1. f-ce# must be toggled low when reading status register data. f-we# must be inactive (high) when reading status register data. a. f-v cc power-up and standby. b. write program or erase setup command. c. write valid address and data (for program) or erase confirm command. d. automated program or erase delay. e. read status register data (srd): reflects completed program/erase operation. f. write read array command. figure 7. ac waveform: flash program and erase operations
e 28f1602c3, 28F3204C3 31 product preview 9.8 flash reset operations ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plrh t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t figure 8. ac waveform: reset operation table 10. reset specifications (1) f-v cc 2.7 v C3.3 v symbol parameter notes min max unit t plph f-rp# low to reset during read (if f-rp# is tied to v cc , this specification is not applicable) 2,4 100 ns t plrh1 f-rp# low to reset during block erase 3,4 22 s t plrh2 f-rp# low to reset during program 3,4 12 s notes: 1. see section 4.1.4 for a full description of these conditions. 2. if t plph is < 100 ns the device may still reset but this is not guaranteed. 3. if f-rp# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. sampled, but not 100% tested.
28f1602c3, 28F3204C3 e 32 product preview 9.9 sram ac characteristics read operations (1, 4) extended temperature density 2/4 mbit volt 2.7 v C3.3 v # sym parameter note min max unit r1 t rc read cycle time 70 Cns r2 t aa address to output delay C 70 ns r3 t co1, t co2 s-cs 1 #, s-cs 2 to output delay C 70 ns r4 t oe s-oe# to output delay C 35 ns r5 t ba s-ub#, lb# to output delay C 70 ns r6 t lz1 , t lz2 s-cs 1 #, s-cs 2 to output in low z 3 10 C ns r7 t olz s-oe# to output in low z 0 C ns r8 t hz1 , t hz2 s-cs 1 #, s-cs 2 to output in high z 2, 3 0 25 ns r9 t ohz s-oe# to output in high z 2 0 25 ns r10 t oh output hold from address, s-cs 1 #, s-cs 2 , or s-oe# change, whichever occurs first 0Cns r11 t blz s-ub#, s-lb# to output in low z 0 C ns r12 t bhz s-ub#, s-lb# to output in high z 0 25 ns notes: 1. see figure 9 ac waveform: sram read operations . 2. timings of t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. at any given temperature and voltage condition, t hz (max.) is less than and t lz (max.) both for a given device and from device to device interconnection. 4. sampled, but not 100% tested.
e 28f1602c3, 28F3204C3 33 product preview high z valid output address stable data valid device address selection standby addresses (a) v ih v il v ih v il cs 1 # (e 1 ) v ih v il v oh v ol v ih oe# (g) we# (w) data (d/q) ub#, lb# high z v ih v il r1 r2 r4 r3 r6 r7 r8 r9 r10 cs 2 (e 2 ) v ih v il v ih r5 r11 r12 figure 9. ac waveform: sram read operations
28f1602c3, 28F3204C3 e 34 product preview 9.10 sram ac characteristics write operations (1, 2) extended temperature density 2/4 mbit volt 2.7 v C3.3 v # sym parameter note min max unit w1 t wc write cycle time 70 Cns w2 t as address setup to s-we# (s-cs 1 #) and s-ub#, s-lb# going low 40 C ns w3 t wp s-we# (s-cs 1 #) pulse width 3 55 C ns w4 t dw data to write time overlap 30 C ns w5 t aw address setup to s-we# (s-cs 1 #) going high 60 C ns w6 t cw s-ce# (s-we#) setup to s-we# (s-cs 1 #) going high 60 C ns w7 t dh data hold time from s-we# (s-cs 1 #) high 0Cns w8 t wr write recovery 5 0 C ns w9 t bw s-ub#, s-lb# setup to s-we# (s-cs 1 #) going high 60 C ns notes: 1. see figure 10, ac waveform: sram write operations 2. a write occurs during the overlap (t wp ) of low s-cs 1 # and low s-we#. a write begins when s-cs 1 # goes low and s-we# goes low with asserting s-ub# or s-lb# for single byte operation or simultaneously asserting s-ub# and s-lb# for double byte operation. a write ends at the earliest transition when s-cs 1 # goes high and s-we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t wp is measured from s-cs 1 # going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as s-cs 1 # or s-we# going high.
e 28f1602c3, 28F3204C3 35 product preview high z data in address stable device address selection standby addresses (a) v ih v il v ih v il cs 1 # (e 1 ) v ih v il v oh v ol v ih oe# (g) we# (w) data (d/q) ub#, lb# high z v ih v il w1 w8 cs 2 (e 2 ) v ih v il v ih w9 w6 w5 w2 w3 w4 w7 figure 10. ac waveform: sram write operations 9.11 sram data retention characteristics (1) extended temperature sym parameter note min typ max unit test conditions v dr s-v cc for data retention 2 1.5 C 3.3 v cs 1 # 3 v cc1 C 0.2 v i dr deep retention current 2 C 0.2 5 a s-v cc = 1.2 v cs 1 # 3 v cc1 C 0.2 v t sdr data retention set- up time 0 C C ns see data retention waveform t rdr recovery time t rc CCns notes: 1. typical values at nominal s-v cc , t a = +25 c. 2. s-cs 1 # 3 v cc1 C 0.2 v, s-cs 2 3 v cc1 C 0.2 v (s-cs 1 # controlled) or s-cs 2 0.2 v (s-cs 2 controlled)
28f1602c3, 28F3204C3 e 36 product preview v cc 3.0/2.7v cs 1 # (e 1 ) 2.2v v dr cs 2 (e 2 ) gnd v cc 3.0/2.7v 0.4v v dr gnd cs 1 # controlled cs 2 controlled data retention mode t sdr t rdr data retention mode t sdr t rdr figure 11. sram data retention waveform 10.0 migration guide information typically, it is important to discuss migration compatibility between footprint between a new product and existing products. in this specific case, the stacked csp allows the system desi gner to remove two separate memory footprints for individual flash and sram and replace them with a single footprint, thus resulting in an overall reduction in board space required. this implies that a new printed circuit board would be used to take advantage of this feature. since the flash in stacked-csp shares the same features as the advanced+ boot block features, conversions from the advanced boot block are described in ap-658 designing for upgrade to the advanced+ boot block flash memory, order number 292216 . please contact your local intel representation for detailed information about specific flash + sram system migrations. 11.0 system design considerations this section contains information that would have been contained in a product design guide in earlier generations. in an effort to simplify the amount of documentation, relevant system design considerations have been combined into this document. 11.1 background the new intel advanced+ boot block stacked chip scale package combines the features of the advanced+ boot block flash memory architecture with a low-power sram to achieve an overall reduction in system board space. this enables applications to integrate security with simple software and hardware configurations, while also combining the system sram and flash into one common footprint. this section discusses how to take full advantage of the new 3 volt advanced+ boot block stacked chip scale package.
e 28f1602c3, 28F3204C3 37 product preview 11.1.1 flash + sram footprint integration the stacked chip scale package memory solution can be used to replace a subset of the memory subsystem within a design. where a previous design may have used two separate footprints for sram and flash, you can now replace with the industry standard i-ballout of the stacked csp device. this allows for an overall reduction in board space, which allows the design to integrate both the flash and the sram into one component. 11.1.2 advanced+ boot block flash memory features advanced+ boot block adds the following new features to intel ? advanced boot block architecture: instant, individual block locking provides software/hardware controlled, independent locking/unlocking of any block with zero latency to protect code and data. a 128-bit protection register enables system security implementations. improved 12 v production programming simplifies the system configuration r equired to implement 12 v fast programming common flash interface (cfi) provides component information on the chip to allow software-independent device upgrades for more information on specific advantages of the advanced+ boot block flash memory, please see ap-658 designing with the advanced+ boot block flash memory architecture . 11.2 flash control considerations the flash device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, f-v pp or f-v cc , powers-up first. example flash power supply configurations are shown in figure 12. 11.2.1 f-rp# connected to system reset the use of f-rp# during system reset is important with automated program/erase devices since the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting f-rp# to the system cpu reset# si gnal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when f-v cc voltages are above v lko . since both f-we# and f-ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two- step command sequences. the device is also disabled until f-rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (f-rp# connected to system powerg ood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 11.2.2 f-v cc , f-v pp and f-rp# transition the cui latches commands as issued by system software and is not altered by f-v pp or f-ce# transitions or wsm actions. its default state upon power-up, after exit from reset mode or after f-v cc transitions above v lko (lockout voltage), is read array mode. after any program or block erase operation is complete (even after f-v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired.
28f1602c3, 28F3204C3 e 38 product preview v cc v pp 12 v fast programming absolute write protection with v pp v pplk system supply 12 v supply 10 k w v cc v pp system supply 12 v supply low voltage and 12 v fast programming v cc v pp system supply prot# (logic signal) v cc v pp system supply low-voltage programming low-voltage programming absolute write protection via logic signal (note 1) note: 1. a resistor can be used if the f-v cc supply can sink adequate current based on resistor value. figure 12. example power supply configurations 11.3 noise reduction stacked-csp memorys power switching characteristics require careful device decoupling. system designers should consider three supply current issues for both the flash and sram: 1. standby current levels (i ccs ) 2. read current levels (i ccr ) 3. transient peaks produced by falling and rising edges of f-ce#, s-cs 1 #, and s-cs 2 . transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between each f-v cc /s-v cc and gnd, and between its f-v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. noise issues within a system can cause devices to operate erratically if it is not adequately filtered. in order to avoid any noise interaction issues within a system, it is recomm ended that the design contain the appropriate number of decoupling capacitors in the system. noise issues can also be r educed if leads to the device are kept very short, in order to reduce inductance. decoupling capacitors between v cc and v ss reduce voltage spikes by supplying the extra current needed during switching. placing these capacitors as close to the device as possible reduces line inductance. the capacitors should be low inductance capacitors; surface mount capacitors typically exhibit lower inductance.
e 28f1602c3, 28F3204C3 39 product preview s-v ssq d10 sram die flash die substrate xx s-x f-x substrate connection to package ball sram die bond pad connection flash die bond pad connection s-v ccq s-v cc s-v ss f-v pp f-v ssq f-v cc f-v ccq f-v ss h8 a9 d9 e4 d3 notes: 1. substrate connections refer to ballout locations shown in figure 1. 2. 0.1 m f capacitors should be used with d9, d10 and e4. figure 13. typical flash+sram substrate power and ground connections figure 13 shows that the flash v cc and v ccq lines are tied together within the substrate; the diagram also shows that the sram v cc and v ccq lines are ties together within the substrate of the package. because of this, it is highly recommended that systems use a 0.1 m f capacitor for each of the d9, d10, and e4 grid ballout locations (see figure 1 for ballout). these capacitors are necessary to avoid undesired conditions created by excess noise. 11.4 simultaneous operation the term simultaneous operation in used to describe the ability to read or write to the sram while also programming or erasing flash. in addition, f-ce#, s-cs 1 # and s-cs should not be enabled at the same time. simultaneous operation of the can be summarized by the following: flash program or erase operations during and sram read/write are allowed simultaneous bus operations between the flash and sram are not allowed (bus contention) 11.4.1 sram operation during flash busy this functionality provides the ability to use both the flash and the sram at the same time within a system, similar to the operation of two devices with separate footprints. this operation can be achieved by following the appropriate timing constraints within a system.
28f1602c3, 28F3204C3 e 40 product preview 11.4.2 simultaneous bus operations operations that require both the sram and flash to be in active mode are disallowed. an example of these cases would include simultaneous reads on both the flash and sram, which would result in contention for the data bus, and thus would not produce the intended result. finally, a read of one device a write of the other similar to the conditions of direct memory access (dma) operation are also not within the recommended operating conditions. 11.5 printed circuit board notes the intel stacked csp will save significant space on your pcb by combining two chips into one bga style package. intel stacked csp has a 0.8 mm pitch that can be routed on your printed circuit board with conventional design rules. trace widths of 0.127 mm (0.005 inches) are typical. unused balls in the center of the package are not populated to further increase the routing options. standard surface mount process and equipment can be used for the intel stacked csp. land pad diameter: 0.35 mm (0.0138 in) solder mask opening: 0.50 mm (0.0198 in) trace width: 0.127 mm (0.005 in) trace spaces: 0.160 mm (0.00625 in) via capture pad: 0.51 mm (0.020 in) via drill size: 0.25 mm (0.010 in) note: top view figure 14. standard pcb design rules can be used with stacked csp devices 11.6 system design notes summary the new advanced+ boot block stacked csp allows higher levels of memory component integration. different power supply configurations can be used within the system to achieve different objectives. at least three 0.1 m f capacitors should be used to decouple the devices within a system. sram reads or writes during a flash program or erase are supported operations. standard printed circuit board technology can be used.
e 28f1602c3, 28F3204C3 41 product preview 12.0 ordering information r d 2 8 f 1 6 0 c 3 t 9 0 package rd = 8x12 ball matrix csp product line designator for all intel ? flash products access speed (ns) 16 mbit = 90, 110 32 mbit = 110 product family c3 = 3 v advanced+ boot block v cc = 2.7 v - 3.6 v v pp = 1.65 v - 3.6 v or 11.4 v - 12.6 v flash device density 320 = x16 (32 mbit) 160 = x16 (16 mbit) t = top blocking b = bottom blocking 2 sram device density 4 = x16 (4 mbit) 2 = x16 (2 mbit) order valid combinations (all extended temperature) rd28f1602c390 rd28f1602c3110 rd28F3204C3110 note: 90 ns access speed available at production (high volume). 13.0 additional information (1,2) order number document/tool 210830 flash memory databook 292216 ap-658 designing for upgrade to the advanced+ boot block flash memory 292215 ap-657 designing with the advanced+ boot block flash memory architecture contact your intel representative flash data integrator (fdi) software developers kit 297874 fdi interactive: play with intels flash data integrator on your pc notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com or http://developer.intel.com for technical documentation and tools.
28f1602c3, 28F3204C3 e 42 product preview appendix a program/erase flowcharts start write 40h program address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error programming error attempted program to locked block - aborted program successful sr.3 = sr.4 = sr.1 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases where multiple bytes are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1 0 1 0 1 0 command program setup program comments data = 40h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.1 1 = attempted program to locked block - program aborted read status register data toggle ce# or oe# to update status register data standby check sr.4 1 = v pp program error figure 15. automated word programming flowchart
e 28f1602c3, 28F3204C3 43 product preview start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 read array data from block other than the one being programmed. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation command 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write write read read standby standby write data = 70h addr = x command program suspend read status read array program resume figure 16. program suspend/resume flowchart
28f1602c3, 28F3204C3 e 44 product preview start write 20h write d0h and block address read status register sr.7 = full status check if desired block erase complete full status check procedure bus operation write write standby repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last write operation to reset device to read array mode. bus operation standby sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend erase suspend erase loop 1 0 standby command erase setup erase confirm comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pp range error command sequence error block erase successful sr.3 = sr.4,5 = 1 0 1 0 block erase error sr.5 = 1 0 attempted erase of locked block - aborted sr.1 = 1 0 read status register data toggle ce# or oe# to update status register data standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block - erase aborted figure 17. automated block erase flowchart
e 28f1602c3, 28F3204C3 45 product preview start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh read array data erase completed done reading yes write ffh write d0h erase resumed read array data 0 1 read array data from block other than the one being erased. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = x bus operation write standby write read standby read command 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write data = 70h addr = x command erase suspend read status read array erase resume figure 18. erase suspend/resume flowchart
28f1602c3, 28F3204C3 e 46 product preview start write 60h (configuration setup) no comments data = 60h addr = x write 90h (read configuration) read block lock status locking change confirmed? locking change complete bus operation write command write 01h, d0h, or 2fh write write data= 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr=within block to lock command config. setup lock, unlock, or lockdown data = 90h addr = x write (optional) read configuration block lock status data addr = second addr of block read (optional) block lock status confirm locking change on dq 1 , dq 0 . (see block locking state table for valid combinations.) standby (optional) optional write ffh (read array) figure 19. locking operations flowchart
e 28f1602c3, 28F3204C3 47 product preview start write c0h (protection reg. program setup) write protect. register address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error protection register programming error attempted program to locked register - aborted program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = full status check procedure bus operation write write standby protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1, 1 0,1 1,1 command protection program setup protection program comments data = c0h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments sr.1 sr.3 sr.4 0 1 1 v pp low 0 0 1 prot. reg. prog. error 1 0 1 register locked: aborted read status register data toggle ce# or oe# to update status register data standby figure 20. protection register programming flowchart
28f1602c3, 28F3204C3 e 48 product preview appendix b cfi query structure this appendix defines the data structure or database returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. b.1 query structure output the query database allows system software to gain information for controlling the flash com ponent. this section describes the devices cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest-order data outputs (dq 0-7 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, q and r in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. thus, the device outputs ascii q in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the h suffix has been dropped. in addition, since the upper byte of word-wide devices is always 00h, the leading 00 has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table b1. summary of query structure output as a function of device and mode device hex offset code ascii value device addresses 10: 51 q 11: 52 r 12: 59 y
e 28f1602c3, 28F3204C3 49 product preview table b2. example of query structure output of x16 and x8 devices word addressing byte addressing offset hex code value offset hex code value a 15 Ca 0 d 15 Cd 0 a 7 Ca 0 d 7 Cd 0 0010h 0051 q 10h 51 q 0011h 0052 r 11h 52 r 0012h 0059 y 12h 59 y 0013h p_id lo prvendor 13h p_id lo prvendor 0014h p_id hi id # 14h p_id lo id # 0015h p lo prvendor 15h p_id hi id # 0016h p hi tbladr 16h ... ... 0017h a_id lo altvendor 17h 0018h a_id hi id # 18h ... ... ... ... b.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. the structure sub-sections and address locations are summarized below. table b3. query structure (1) offset sub-section name description 00h manufacturer code 01h device code (ba+2)h (2) block status register block-specific information 04-0fh reserved reserved for vendor-specific information 10h cfi query identification string command set id and vendor data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p (3) primary intel - specific extended query table vendor - defined additional information specific to the primary vendor algorithm notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = the beginning location of a block address (e.g., 08000h is the beginning location of block 1 when the block size is 32 kword). 3. offset 15 defines p which points to the primary intel - specific extended query table.
28f1602c3, 28F3204C3 e 50 product preview b.3 block lock status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the v cc supply was not accidentally removed during an erase operation. this bit is only reset by issuing another erase operation to the block. the block status register is accessed from word address 02h within each block. table b4. block status register offset length description add. value (ba+2)h (1) 1 block lock status register ba+2: --00 or --01 bsr.0 block lock status 0 = unlocked 1 = locked ba+2: (bit 0): 0 or 1 bsr.1 block lock-down status 0 = not locked down 1 = locked down ba+2: (bit 1): 0 or 1 bsr 2 C7: reserved for future use ba+2: (bit 2C7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is the beginning location of block 1 in word mode.) b.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table b5. cfi identification offset length description add. hex code value 10h 3 query-unique ascii string qry 10 --51 q 11: --52 r 12: --59 y 13h 2 primary vendor command set and control interface id code. 13: --03 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --35 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00
e 28f1602c3, 28F3204C3 51 product preview b.5 system interface information table b6. system interface information offset length description add. hex code value 1bh 1 v cc logic supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts 1c: --36 3.6 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts 1d: --b4 11.4 v 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts 1e: --c6 12.6 v 1fh 1 n such that typical single word program time-out = 2 n s 1f: --05 32 s 20h 1 n such that typical max. buffer write time-out = 2 n s 20: --00 na 21h 1 n such that typical block erase time-out = 2 n ms 21: --0a 1s 22h 1 n such that typical full chip erase time-out = 2 n ms 22: --00 na 23h 1 n such that maximum word program time-out = 2 n times typical 23: --04 512s 24h 1 n such that maximum buffer write time-out = 2 n times typical 24: --00 na 25h 1 n such that maximum block erase time-out = 2 n times typical 25: --03 8s 26h 1 n such that maximum chip erase time-out = 2 n times typical 26: --00 na
28f1602c3, 28F3204C3 e 52 product preview b.6 device geometry definition table b7. device geometry definition offset length description code see table below 27h 1 n such that device size = 2 n in number of bytes 27: 28h 2 flash device interface: x8 async x16 async x8/x16 async 28: --01 x16 28:00,29:00 28:01,29:00 28:02,29:00 29: --00 2ah 2 n such that maximum number of bytes in write buffer = 2 n 2a: --00 0 2b: --00 2ch 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --02 2 2dh 4 erase block region 1 information 2d: bits 0C15 = y, y+1 = number of identical-size erase blocks 2e: bits 16C31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0C15 = y, y+1 = number of identical-size erase blocks 32: bits 16C31 = z, region erase block(s) size are z x 256 bytes 33: 34: device geometry definition address 16 mbit 32 mbit Cb Ct Cb Ct 27: --15 --15 --16 --16 28: --01 --01 --01 --01 29: --00 --00 --00 --00 2a: --00 --00 --00 --00 2b: --00 --00 --00 --00 2c: --02 --02 --02 --02 2d: --07 --1e --07 --3e 2e: --00 --00 --00 --00 2f: --20 --00 --20 --00 30: --00 --01 --00 --01 31: --1e --07 --3e --07 32: --00 --00 --00 --00 33: --00 --20 --00 --20 34: --01 --00 --01 --00
e 28f1602c3, 28F3204C3 53 product preview b.7 intel-specific extended query table certain flash features and commands are optional. the intel - specific extended query table specifies this and other similar types of information. table b8. primary-vendor specific extended query offset (1) p = 35h length description (optional flash features and commands) add. hex code value (p+0)h 3 primary extended query table 35: --50 p (p+1)h unique ascii string pri 36: --52 r (p+2)h 37: --49 i (p+3)h 1 major version number, ascii 38: --31 1 (p+4)h 1 minor version number, ascii 39: --30 0 (p+5)h 4 optional feature and command support (1=yes, 0=no) 3a: --66 (p+6)h bits 9 C31 are reserved; undefined bits are 0. if bit 31 is 3b: --00 (p+7)h 1 then another 31 bit field of optional features follows 3c: --00 (p+8)h at the end of the bit-30 field. 3d: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 page mode read supported bit 7 = 0 no bit 8 synchronous read supported bit 8 = 0 no (p+9)h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1C7 reserved; undefined bits are 0 3e: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h 2 block status register mask 3f: --03 (p+b)h bits 2C15 are reserved; undefined bits are 0 40: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes (p+c)h 1 v cc logic supply highest performance program/erase voltage bits 0 C3 bcd value in 100 mv bits 4C7 bcd value in volts 41: --33 3.3 v (p+d)h 1 v pp optimum program/erase supply voltage bits 0C3 bcd value in 100 mv bits 4C7 hex value in volts 42: --c0 12.0 v
28f1602c3, 28F3204C3 e 54 product preview table b9. protection register information offset (1) p = 35h length description (optional flash features and commands) add. hex code value (p+e)h 1 number of protection register fields in jedec id space. 00h, indicates that 256 protection bytes are available 43: --01 01 (p+f)h 4 protection field 1: protection description 44: --80 80h (p+10)h this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device-unique serial numbers. others are user programmable. bits 0C15 point to the protection register lock byte, the sections first byte. the following bytes are factory pre-programmed and user- programmable. 45: --00 00h (p+11)h bits 0C7 = lock/bytes jedec-plane physical low address bits 8C15 = lock/bytes jedec -plane physical high address bits 16C23 = n such that 2 n = factory pre- programmed bytes bits 24C31 = n such that 2 n = user programmable bytes 46: --03 8 byte (p+12)h 47: --03 8 byte (p+13)h reserved for future use 48: notes: 1. the variable p is a pointer which is defined at cfi offset 15h.
e 28f1602c3, 28F3204C3 55 product preview appendix c word-wide memory map diagrams 16-mbit, and 32-mbit word-wide memory flash addressing top boot bottom boot size (kw) 16m 32m size (kw) 16m 32m 4 ff000-fffff 1ff000-1fffff 32 1f8000-1fffff 4 fe000-fefff 1fe000-1fefff 32 1f0000-1f7fff 4 fd000-fdfff 1fd000-1fdfff 32 1e8000-1effff 4 fc000-fcfff 1fc000-1fcfff 32 1e0000-1e7fff 4 fb000-fbfff 1fb000-1fbfff 32 1d8000-1dffff 4 fa000-fafff 1fa000-1fafff 32 1d0000-1d7fff 4 f9000-f9fff 1f9000-1f9fff 32 1c8000-1cffff 4 f8000-f8fff 1f8000-1f8fff 32 1c0000-1c7fff 32 f0000-f7fff 1f0000-1f7fff 32 1b8000-1bffff 32 e8000-effff 1e8000-1effff 32 1b0000-1b7fff 32 e0000-e7fff 1e0000-1e7fff 32 1a8000-1affff 32 d8000-dffff 1d8000-1dffff 32 1a0000-1a7fff 32 d0000-d7fff 1d0000-1d7fff 32 198000-19ffff 32 c8000-cffff 1c8000-1cffff 32 190000-197fff 32 c0000-c7fff 1c0000-1c7fff 32 188000-18ffff 32 b8000-bffff 1b8000-1bffff 32 180000-187fff 32 b0000-b7fff 1b0000-1b7fff 32 178000-17ffff 32 a8000-affff 1a8000-1affff 32 170000-177fff 32 a0000-a7fff 1a0000-1a7fff 32 168000-16ffff 32 98000-9ffff 198000-19ffff 32 160000-167fff 32 90000-97fff 190000-197fff 32 158000-15ffff 32 88000-8ffff 188000-18ffff 32 150000-157fff 32 80000-87fff 180000-187fff 32 148000-14ffff 32 78000-7ffff 178000-17ffff 32 140000-147fff 32 70000-77fff 170000-177fff 32 138000-13ffff 32 68000-6ffff 168000-16ffff 32 130000-137fff 32 60000-67fff 160000-167fff 32 128000-12ffff 32 58000-5ffff 158000-15ffff 32 120000-127fff 32 50000-57fff 150000-157fff 32 118000-11ffff 32 48000-4ffff 148000-14ffff 32 110000-117fff 32 40000-47fff 140000-147fff 32 108000-10ffff 32 38000-3ffff 138000-13ffff 32 100000-107fff 32 30000-37fff 130000-137fff 32 f8000-fffff 0f8000-0fffff 32 28000-2ffff 128000-12ffff 32 f0000-f7fff 0f0000-0f7fff 32 20000-27fff 120000-127fff 32 e8000-effff 0e8000-0effff 32 18000-1ffff 118000-11ffff 32 e0000-e7fff 0e0000-0e7fff 32 10000-17fff 110000-117fff 32 d8000-dffff 0d8000-0dffff 32 08000-0ffff 108000-10ffff 32 d0000-d7fff 0d0000-0d7fff 32 00000-07fff 100000-107fff 32 c8000-cffff 0c8000-0cffff this column continues on next page this column continues on next page
28f1602c3, 28F3204C3 e 56 product preview 16-mbit, and 32-mbit word-wide memory addressing (continued) top boot bottom boot size (kw) 16m 32m size (kw) 16m 32m 32 0f8000-0fffff 32 c0000-c7fff 0c0000-0c7fff 32 0f0000-0f7fff 32 b8000-bffff 0b8000-0bffff 32 0e8000-0effff 32 b0000-b7fff 0b0000-0b7fff 32 0e0000-0e7fff 32 a8000-affff 0a8000-0affff 32 0d8000-0dffff 32 a0000-a7fff 0a0000-0a7fff 32 0d0000-0d7fff 32 98000-9ffff 098000-09ffff 32 0c8000-0cffff 32 90000-97fff 090000-097fff 32 0c0000-0c7fff 32 88000-8ffff 088000-08ffff 32 0b8000-0bffff 32 80000-87fff 080000-087fff 32 0b0000-0b7fff 32 78000-7ffff 78000-7ffff 32 0a8000-0affff 32 70000-77fff 70000-77fff 32 0a0000-0a7fff 32 68000-6ffff 68000-6ffff 32 098000-09ffff 32 60000-67fff 60000-67fff 32 090000-097fff 32 58000-5ffff 58000-5ffff 32 088000-08ffff 32 50000-57fff 50000-57fff 32 080000-087fff 32 48000-4ffff 48000-4ffff 32 078000-07ffff 32 40000-47fff 40000-47fff 32 070000-077fff 32 38000-3ffff 38000-3ffff 32 068000-06ffff 32 30000-37fff 30000-37fff 32 060000-067fff 32 28000-2ffff 28000-2ffff 32 058000-05ffff 32 20000-27fff 20000-27fff 32 050000-057fff 32 18000-1ffff 18000-1ffff 32 048000-04ffff 32 10000-17fff 10000-17fff 32 040000-047fff 32 08000-0ffff 08000-0ffff 32 038000-03ffff 4 07000-07fff 07000-07fff 32 030000-037fff 4 06000-06fff 06000-06fff 32 028000-02ffff 4 05000-05fff 05000-05fff 32 020000-027fff 4 04000-04fff 04000-04fff 32 018000-01ffff 4 03000-03fff 03000-03fff 32 010000-017fff 4 02000-02fff 02000-02fff 32 008000-00ffff 4 01000-01fff 01000-01fff 32 000000-007fff 4 00000-00fff 00000-00fff
e 28f1602c3, 28F3204C3 57 product preview appendix d device id table read configuration addresses and data item address data manufacturer code x16 00000 0089 device code 16-mbit x 16-t x16 00001 88c2 16-mbit x 16-b x16 00001 88c3 32-mbit x 16-t x16 00001 88c4 32-mbit x 16-b x16 00001 88c5 note: other locations within the configuration address space are reserved by intel for future use.
28f1602c3, 28F3204C3 e 58 product preview appendix e protection register addressing word-wide protection register addressing word use a7 a6 a5 a4 a3 a2 a1 a0 lock both 10000000 0 factory 10000001 1 factory 10000010 2 factory 10000011 3 factory 10000100 4 user 10000101 5 user 10000110 6 user 10000111 7 user 10001000 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a 21 Ca 8 = 0.
e 28f1602c3, 28F3204C3 59 product preview appendix f stacked chip scale package mechanical specification a 2 a 1 a y top view: ball down s 1 123456789101112 h g f e d c b a b e s 2 a1 index mark bottom view: ball up e d a1 mechanical note: 72- ball package consists of 8 x 12 solder ball matrix, 8 rows and 12 columns. each row is identified by a number and the column by a letter. each bump location, thus, is designated by row & column combination. example, bump c2 indicates 3rd row and the 2nd column. figure 21. 72-ball stacked-csp: 12 x 8 matrix
28f1602c3, 28F3204C3 e 60 product preview millimeters inches sym min nom max min nom max package height a 1.20 1.30 1. 40 0.047 0.051 0.055 standoff a1 0.30 0.35 0.40 0.012 0.014 0.016 package body thickness a2 0.92 0.97 1.02 0.036 0.038 0.040 ball lead diameter b 0.325 0.40 0.475 0.013 0.016 0.019 package body length C 16 mb/2 mb d 9.90 10.00 10.10 0.429 0.433 0.437 package body width C 16 mb/2 mb e 7.90 8.00 8.10 0.311 0.315 0.319 package body length C 32 mb/4 mb d 11.90 12.00 12.10 0.469 0.472 0.476 package body width C 32 mb/4 mb e 7.90 8.00 8.10 0.311 0.315 0.319 pitch e 0.80 0.031 seating plane coplanarity y 0.1 0.004 corner to first bump distance C 16 mb/2 mb s1 1.10 1.20 1.30 0.0433 0.0472 0.0512 corner to first bump distance C 16 mb/2 mb s2 0.50 0.60 0.70 0.0197 0.0236 0.0276 corner to first bump distance C 32 mb/ 4mb s1 1.10 1.20 1.30 0.0433 0.0472 0.0512 corner to first bump distance C 32 mb/ 4mb s2 1.50 1.60 1.70 0.0591 0.0630 0.0669
e 28f1602c3, 28F3204C3 61 product preview appendix g stacked chip scale package media information device pin 1 tray chamfer tray notes: drawing is not to scale and is only designed to show orientation of devices. figure 22. stacked csp device in tray orientation (8 x 10 mm and 8 x 12 mm)
28f1602c3, 28F3204C3 e 62 product preview device pin 1 tape figure 23. stacked csp device in 24 mm tape (8 x 10 mm and 8 x 12 mm)

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